In recent years, high integration of a semiconductor device is in progress. If a plurality of highly-integrated semiconductor devices is disposed within a horizontal plane and if the semiconductor devices are formed into a final product by connecting them with wiring lines, the length of the wiring lines becomes longer. Thus, there is a fear that the resistance of the wiring lines grows larger and the wiring delay becomes severe.
Under the circumstances, there has been proposed the use of a three-dimensional integration technology that three-dimensionally stacks semiconductor devices. In this three-dimensional integration technology, two semiconductor wafers (hereinafter referred to as “wafers”) are joined through the use of, e.g., a joining system. For example, the joining system includes a surface modification device (a surface activation device) configured to modify the surfaces of the wafers to be joined, a surface hydrophilization device configured to hydrophilize the surfaces of the wafers modified by the surface modification device, and a joining device configured to join the wafers whose surfaces are hydrophilized by the surface hydrophilization device. In this joining system, the surface hydrophilization device supplies pure water to the surfaces of the wafers to thereby hydrophilize the surfaces of the wafers. Thereafter, the joining device joins the wafers with a Van der Waals force and a hydrogen bond (an intermolecular force).
In the joining device, one wafer (hereinafter referred to as an “upper wafer”) is held by an upper chuck and another wafer (hereinafter referred to as a “lower wafer”) is held by a lower chuck installed below the upper chuck. In this state, the upper wafer and the lower wafer are joined together. In order to increase the Van der Waals force and to promote the hydrogen bond at this time, it has been proposed to install cooling mechanisms in the upper chuck and the lower chuck and to join the upper wafer and the lower wafer while cooling them.
However, this joining device fails to control and manage the temperature of the upper wafer not yet held in the upper chuck and the temperature of the lower wafer not yet held in the lower chuck. For that reason, there is a fear that, prior to the upper wafer and the lower wafer being held in the upper chuck and the lower chuck, variations in the temperatures of the upper wafer and the lower wafer may occur due to various external causes. In particular, the upper wafer and the lower wafer are independently transferred to the upper chuck and the lower chuck. Therefore, the standby time is not consistent and variations in the standby time easily occur.
In the meantime, it is known that, if the temperatures of the upper wafer and the lower wafer are changed, the shapes thereof are also changed. In the case of, e.g., a silicon wafer, if the temperature thereof increases 1 degree C., the diameter thereof increases several micrometers due to thermal expansion.
When joining the upper wafer and the lower wafer, it is required that the joining position of the upper wafer and the lower wafer be controlled at a micrometer level. If variations exist in the temperatures of the upper wafer and the lower wafer as mentioned above and if the variations caused by the temperature variations exist in the dimensions and shapes of the upper wafer and the lower wafer, it is impossible to accurately control the joining position. Consequently, there is a fear that, when joining the upper wafer and the lower wafer, they may be joined in a misaligned state.
As an example, it is conceivable to individually adjust the temperatures of the upper wafer and the lower wafer through the use of cooling mechanisms for the upper chuck and the lower chuck. However, in this case, the temperature adjustment is performed after the upper wafer and the lower wafer are held in the upper chuck and the lower chuck. Thus, time is required in the temperature adjustment. For that reason, the timing of starting the adjustment of the positions of the upper wafer and the lower wafer are delayed. This makes it impossible to rapidly perform the position adjustment.
As pointed out above, there is room for improvement in the wafer joining process of the related art.